Open CAD Tools

Open CAD tools for Hardware Designing and Validation

Libraries

Some usefull libraries that you can use in your designs.

• freeCores (Opencores on Github)
• common_cells
• Math

Verilog simulators

Some usefull verilog simulators that you can use freely.

• IVerilog

  $ iverilog *.v -o a.out # compile
  $ vvp a.out # run
  

• Verilator

Hardware Synthesis

Open source hardware synthesize tools

• Yosys

Route and Placement

• nextpnr

Signal Visualizers

• GTKWave
• WaveTrace - (+vscode)
• vcdrom - online drag and drop

Formal Verification Tools

• Hardware Descriptions
  • SymbiYosys
  • rtvl ( +racket +rosette)
  • EBMC
• Firmware
  • serval ( +racket +rosette)

Concolic Testing

• ISV

Format Conversion

Some tricks related to file type conversions

• System Verilog to Verilog : sv2v

Heirarchy Flatten / SMT conversion wth Yosys

This simple app will generate the code snippet that you can run directly on the terminal environment for following conversions.

• Heirarchy flatten of Verilog designs
• Verilog to SMT2 (Satisfiability modulo theories) conversion
• Verilog to blif (Berkeley Logic Interchange Format) conversion

If the design is contained in multiple Verilog files concatenate them into one file before the conversion by below command

cat *.v > DESIGN.v

Then generate the code from below app and run the generated command directly from the terminal.

IDEs

• TerosHDL (+vscode)