I am involved in research in systems security validation and verification. My interests lie at the thin intersection of Electronics Engineering (EE) and Computer Science Engineering (CSE). Currently, my focus revolves around hardware-firmware validation, applied cryptography, trusted execution and side-channel analysis. Some of the projects which are not affiliated are available for the public at my github. Throughout my diverse range of projects, I have gained experience working with various CAD tools. Some of the tools I have utilized include Synopsys tools (VCS, DC, TMAX), Yosys Open Source EDA (Yosys, nextpnr, icestorm), Xilinx tools (Vivado, ISE), Intel Quartus, ModelSim, Icarus Verilog, symbolic verification tools (Racket + Rosette + Z3), Altium, and Solidworks. Apart from my professional pursuits, I am an avid automotive enthusiast. I thoroughly enjoy working on cars and drones, pushing them to their limits in the field to assess their performance. During my free time, I love diving into awesome activities like swimming, kayaking, and exploring the epic world of cars.

Systems Security Hardware Verification Firmware Verification Side-channel Analysis Applied Cryptography Root-of-Trust Symbolic Execution

Education


University of Florida 🇺🇸
Doctor of Philosophy, Computer Engineering 2021-Present

University of Moratuwa 🇱🇰
Honours Degree of Bachelor of the Science of Engineering 2015-2019
Specialisation: Computer Science and Engineering (ICE)

Updates

  • Excited to share the acceptance of the paper, 'EvilCS: An Evaluation of Information Leakage through Context Switching on Security Enclaves' at DateConference 2024! Kudos to my co-authors Richard Bachmann and Dr. Prabhat Mishra for their contributions. Read more...
  • SRC is proud to support the research of future innovators like Aruna Jayasena, a third-year Ph.D. candidate at the University of Florida! His primary area of research is on systems security validation and verification. Aruna's journey into hardware Read more...
  • Thrilled to share our paper 'TVLA*: Test Vector Leakage Assessment on Hardware Implementations of Asymmetric Cryptography Algorithms' accepted in IEEE TVLSI! Explore pre-silicon side channel leakage evaluation of public key cryptography Read more...
  • Excited to announce that our paper titled 'Scalable Detection of Hardware Trojans using ATPG-based Activation of Rare Events' has been accepted in IEEE TCAD! Read more...
  • 🚀🔬 Delighted to unveil library crafted for the world's tiniest opensource Ice-Sugar-nano FPGA! 🌐🔗 Get it here: 'https://github.com/Archfx/ice40lib'